Prof. Dr. Alexander Jesser

Veröffentlichungen

  • R. Eschenweck, D. Unger, Ch. Kraft, A. Jesser, "Developing Power Line Communications for Smart Street Lighting", 23. Internationale Wissenschaftliche Konferenz Mittweida (IWKM 2014), Mittweida, Deutschland, November 2014.
  • S. Lämmermann, A. Jesser, A. Viehl, J. Ruf, L. Hedrich, T. Kropf, W. Rosenstiel,. "Towards Assertion-Based Verification of Heterogeneous System Designs", The Design, Automation and Test Conference in Europe (DATE’10), Dresden, pp. 1171- 1176, März 2010.
  • S. Lämmermann, A. Jesser, M. Rathegeber, J. Ruf, L. Hedrich, T. Kropf, W. Rosenstiel. "Checking Heterogeneous Signal Characteristics Applying Assertion- Based Verification", Formal Verification of Analog Circuits (FAC'09), Grenoble, Frankreich, Juni 2009.
  • S. Lämmermann, A. Jesser, R. Weiss, J. Ruf, T. Kropf, L. Hedrich, W. Rosenstiel. "An Assertion-Based Verification Methodology for SystemC-AMS Designs", The 15thWorkshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI’09), Okinawa, Japan, pp. 434-439, März 2009.
  • S. Lämmermann, A. Pacholik, A. Jesser, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel. "Improving Mixed-Signal Verification by Assertions Based Design", The 16thIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC’08), Rhodos, Griechenland, pp. 144-147, Oktober 2008.
  • A. Jesser, L. Hedrich. "A Symbolic Approach for Mixed-Signal Model Checking", The 13thAsia and South Pacific Design Automation Conference (ASP-DAC’08), Seoul, Korea, pp. 404-409, Januar 2008.
  • A. Jesser, S. Lämmermann, A. Pacholik, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel. "Analog Simulation Meets Digital Verification - A Formal Assertion Approach for Mixed-Signal Verification", The 14th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’07), Hokkaido, Japan, pp. 507-514, Oktober 2007.
  • S. Steinhorst, A. Jesser, L. Hedrich. "Advanced Property Specification for Model Checking of Analog Systems", 9. ITG/GMM-Fachtagung Analog (Analog'06), Dresden, Deutschland, pp. 63-68, September 2006.
  • A. Jesser, M. Wedler, L. Hedrich, W. Kunz. "A case study on applying bounded model checking to analog circuit verification", 9. GI/ITG/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'06), Dresden, Deutschland, pp. 106-113, Februar 2006.
  • S. Urquijo, G. Rohmer, J. Garcia-Blanch, A. Jesser, "Wideband Architecture for Future Navigation Systems", The 7th European Navigation Conference (ENC- GNSS’03), Graz, Österreich, pp. 106-113, April 2003.
  • C. Amelunxen, Ch. Budnik, S. Burmester, M. Grünwald, H. Höschen, A. Jesser, K. Pöhland, N. Sevilmis, C. Carsten;  "Kooperatives autonomes Verhalten am Beispiel eines Clusteralgorithmus",  Heinz Nixdorf Institut, Schaltungstechnik, Universität Paderborn, Sep. 2000.

Journals

  • A. Jesser, S. Lämmermann, A. Pacholik, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel. "Advanced Assertion-Based Design for Mixed-Signal Verification", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on “VLSI Design and CAD Algorithms, Vol. E91–A, No. 12, pp. 3548-3555, Dezember 2008.

Bücher

  • A. Jesser. "Mixed-Signal Circuit Verification Using Symbolic Model Checking Techniques", Dissertation, Universität Frankfurt a. M., ISBN 978-3-89963-841-7, Verlag Dr. Hut, Oktober 2008.